1. Field of the Invention
The invention relates generally to semiconductor structures. More particularly, the invention relates to enhanced structural integrity of multilayer spacers fabricated within semiconductor structures.
2. Description of the Related Art
In addition to active semiconductor devices and passive semiconductor devices such as resistors, transistors, diodes and capacitors, semiconductor structures often include dielectric structures and conductor structures. The dielectric structures and conductor structures typically serve a purpose of defining and providing a signal propagation pathway for connection and interconnection of the active semiconductor devices and the passive semiconductor devices.
A fairly common structure that is used as an adjunct with other semiconductor structures is a spacer. Spacers may be formed of conductor materials, semiconductor materials and dielectric materials. Spacers may also be formed as laminates or composites of the foregoing materials. Spacers are typically formed using a blanket spacer material layer deposition and a subsequent anisotropic etchback method. Using the foregoing method, a spacer is formed with a characteristic inward pointing tip with respect to a topographic feature that the spacer adjoins over a substrate.
Dielectric spacers in particular provide value within the context of isolating topographic conductor structures within semiconductor structures. The topographic conductor structures may include, but are not limited to interconnect conductor layers, as well as gate electrode conductor layers.
Spacers are clearly an important component within semiconductor structures. However, spacers are not always readily fabricated with optimal properties within semiconductor structures. In particular, optimal spacer profiles are often difficult to achieve within semiconductor structures.
Various semiconductor structures having desirable properties, and methods for fabrication thereof, are known in the semiconductor fabrication art.
For example, Bartlau et al., in U.S. Pat. No. 6,541,351, teaches a method for fabricating an isolation region within a semiconductor substrate with inhibited divot formation at a junction of the isolation region with the semiconductor substrate. To realize the foregoing result, a particular embodiment of the disclosed invention uses a chemical oxide removal (COR) etchant that selectively etches a thermal oxide material formed upon the semiconductor substrate with respect to a deposited oxide material that comprises the adjoining isolation region.
In addition, Doris et al., in U.S. Pub. No. 2005/0003589, teaches an ultra-thin channel semiconductor device within a semiconductor-on-insulator substrate absent a polysilicon stringer beneath the ultra-thin channel semiconductor device. To realize the foregoing result, the disclosed invention uses a chemical oxide removal (COR) etchant for selectively removing a thermal silicon oxide pad oxide layer absent lateral etching of a buried dielectric layer, to thus avoid an undercut of the buried dielectric layer beneath the surface semiconductor layer within the semiconductor structure.
Further, Boyd et al., in U.S. Pub. No. 2005/0116289, teaches an ultra-thin channel field effect transistor structure within a semiconductor-on-insulator (SOI) substrate, and a method for fabricating the same. To realize the foregoing result, the method uses a self-aligned oxygen ion implant method for fabricating the ultra-thin channel, optionally in conjunction with a chemical oxide removal (COR) etchant for removing a pad oxide layer absent damage to the ultra-thin channel.
Finally, Doris et al., in U.S. Pub. No. 2006/0001095, teaches a method for fabricating a fully depleted semiconductor-on-insulator (SOI) field effect transistor where electrical property drift, such as threshold voltage drift, is minimized. To realize the foregoing result, the disclosed invention uses a chemical oxide removal (COR) etchant for recessing a channel within the field effect transistor.
Additional uses for chemical oxide removal (COR) etchants are also taught within: (1) Boyd et al., in U.S. Pub. No. 2005/0118826 (a chemical oxide removal (COR) pre-clean surface preparation used when fabricating an ultra-thin silicon metal oxide semiconductor field effect transistor device); and (2) Geiss et al., in U.S. Pub. No. 2006/0017066 (a chemical oxide removal (COR) etchant used when fabricating a bipolar complementary metal oxide semiconductor (BiCMOS) structure).
Semiconductor structure and device dimensions are certain to continue to decrease. As a result thereof, desirable are spacers that may be fabricated with enhanced performance and enhanced properties, particularly with respect to spacer profile.